CPSC 2310 - DAY 18
OCTOBER 14, 2016

================================================================================

Pass by Value
Pass by Reference

	     ARRAY A
	+---------------+
	|		|
	|		|
	+---------------+
	|		|
	|		|
	+---------------+
	|		|
	|		|
	+---------------+
	|		|
	|		|
	+---------------+

ARM LOAD/STORE INSTRUCTIONS
---------------------------

	>Single register data transfer (LDR/STR)
	>Block data transfer (LDM/STM)
	>Single Data Swap (SWP)

LDR	STR	Word

LDRB	STRB	Byte

LDRH	STRH	Halfword


Syntax:
	LDR R0, [R1]
	STR R0, [R1]
	LDREQB R0, [R1]

Data Transfer: Memory to Register
---------------------------------

To transfer a word of data, we need to specify two things

	>Register r0-r15
	>Memory address: more difficult
		.Think of memory as a one dimensional array

Two types of addressing modes avaliable in ARM:
	>Pre-indexed addressing: the address is generated immediately
	>Post-indexed addressing: the address generated later replaces base
	register.

[Rn] - the address found in Rn

Register offset:
	ldr r2, [r0,r1]  //add r0 + r1 to find offset

	ldr r0, [r1, r2, lsl #2]  //r1 + r2*4

ARM Addressing Modes - Preindexing with Update

	>[Rn, #imm]!

	Immediate preindexed w/ update
	Address is accessed as is with immediate offset mode, but Rn's value
	updates to become the address accessed

	ldr r2, [r0, r1]!